ChenJianyunp / Posit32-2-exact-multiply-accumulatorLinks
This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
☆17Updated 7 years ago
Alternatives and similar repositories for Posit32-2-exact-multiply-accumulator
Users that are interested in Posit32-2-exact-multiply-accumulator are comparing it to the libraries listed below
Sorting:
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Open-Source Posit RISC-V Core with Quire Capability☆66Updated 9 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Next generation CGRA generator☆115Updated this week
- ☆15Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Universal number Posit HDL Arithmetic Architecture generator☆64Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆75Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 10 months ago
- FPGA tool performance profiling☆102Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- ☆56Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- ☆67Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 7 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- ☆109Updated 2 months ago
- ☆84Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated this week