This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
☆17Jan 27, 2018Updated 8 years ago
Alternatives and similar repositories for Posit32-2-exact-multiply-accumulator
Users that are interested in Posit32-2-exact-multiply-accumulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal number Posit HDL Arithmetic Architecture generator☆72Jun 24, 2019Updated 7 years ago
- Probably correct posit prototype for python☆18Nov 23, 2019Updated 6 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆46Apr 2, 2025Updated last year
- Open-Source Posit RISC-V Core with Quire Capability☆70May 4, 2026Updated 2 months ago
- The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))☆11Sep 27, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- PACoGen: Posit Arithmetic Core Generator☆81Aug 16, 2019Updated 6 years ago
- A posit arithmetic emulator.☆56Jun 23, 2024Updated 2 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 8 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 3 years ago
- Posit Arithmetic Cores generated with FloPoCo☆30May 8, 2026Updated 2 months ago
- Vector math library using RISC-V vector ISA via C intrinsic☆26Mar 27, 2026Updated 3 months ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Drop-in replacement for IEEE Float☆42Jun 4, 2020Updated 6 years ago
- High-Performance Reproducible BLAS using posit arithmetic☆12Mar 16, 2022Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- Optical Vortex beam can be generated from Spatial Light Modulators (SLM) by uploading required phase mask. This GUI based code can be use…☆10Aug 6, 2018Updated 7 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Updated this week
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- A Deep Learning Framework for the Posit Number System☆31Aug 5, 2024Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11Jul 12, 2023Updated 3 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- ☆14Updated this week
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- OpenCL offline compiler☆21Feb 21, 2016Updated 10 years ago
- Tiny matrix multiplication ASIC with 4-bit math☆12Apr 19, 2024Updated 2 years ago
- note about IC knowledge☆10Sep 7, 2022Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- YOLOv3 implementation in TensorFlow 2.0☆11Feb 19, 2020Updated 6 years ago
- experimental quantized net implementation in chainer☆11Oct 1, 2016Updated 9 years ago