ChenJianyunp / Posit32-2-exact-multiply-accumulator
This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2
☆15Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for Posit32-2-exact-multiply-accumulator
- Open-Source Posit RISC-V Core with Quire Capability☆44Updated this week
- PACoGen: Posit Arithmetic Core Generator☆64Updated 5 years ago
- Universal number Posit HDL Arithmetic Architecture generator☆52Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆17Updated 8 years ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆21Updated 7 months ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆35Updated last year
- ☆13Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- ☆27Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆32Updated 7 months ago
- ☆52Updated 2 years ago
- ☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆20Updated 2 years ago
- ☆16Updated 7 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- DASS HLS Compiler☆27Updated last year