prashanthjonna / Physical-Design-of-ASICs
TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.
☆11Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for Physical-Design-of-ASICs
- Repository for system verilog labs from cadence☆10Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆62Updated 3 years ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆82Updated 3 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆36Updated 7 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Examples and reference for System Verilog Assertions☆82Updated 7 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago
- This is a tutorial on standard digital design flow☆72Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆63Updated 2 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆14Updated 3 years ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- Verilog/SystemVerilog Guide☆54Updated 10 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Introductory course into static timing analysis (STA).☆63Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- RISC-V Verification Interface☆74Updated 2 months ago