TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.
☆17Oct 24, 2021Updated 4 years ago
Alternatives and similar repositories for Physical-Design-of-ASICs
Users that are interested in Physical-Design-of-ASICs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- cadence flow for genus and innovus with UPF added.☆17Jul 3, 2021Updated 4 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 4 years ago
- RTL to GDS via Cadence Tools☆17May 17, 2022Updated 4 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆116Feb 22, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 6 years ago
- Apple Music decryption tool, based on zhaarey/apple-music-alac-atmos-downloader☆18Jun 25, 2024Updated last year
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- Introductory course into static timing analysis (STA).☆108Jul 6, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆37Mar 25, 2020Updated 6 years ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆46Dec 24, 2018Updated 7 years ago
- The complete code is available here with all files except Config folder. To run the project in your system visit the tutorial and watch t…☆28Feb 26, 2024Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…☆104Jan 12, 2021Updated 5 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆42Jun 27, 2021Updated 4 years ago
- Light C++11 graph library☆13Sep 16, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Tensor Belief Propagation - algorithm for approximate inference in discrete graphical models☆12Feb 17, 2020Updated 6 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆35May 20, 2020Updated 6 years ago
- Official implementation of ECCV 2024 paper: "Event-based Mosaicing Bundle Adjustment"☆13Mar 12, 2025Updated last year
- All Digital Phase-Locked Loop☆13May 22, 2023Updated 3 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆56Apr 9, 2026Updated last month
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Introductory course for Perl 5 through examples, geared towards VLSI engineers☆52Oct 1, 2020Updated 5 years ago
- softfloat and softposit in Python☆15Aug 2, 2019Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆88Jun 12, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆22Jun 1, 2025Updated 11 months ago
- ☆47Feb 6, 2025Updated last year
- ☆13Jul 10, 2024Updated last year
- Sum-Product Networks (SPNs) for Robust Automatic Speaker Identification.☆11Aug 30, 2020Updated 5 years ago
- Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.☆12Sep 29, 2022Updated 3 years ago
- Lossless compression using Probabilistic Circuits☆16Mar 10, 2022Updated 4 years ago
- [WSDM 2023] This is the official PyTorch implementation for the paper: "Directed Acyclic Graph Factorization Machines for CTR Prediction …☆18Mar 5, 2023Updated 3 years ago