Alternatives and similar repositories for qoi-fpga

Users that are interested in qoi-fpga are comparing it to the libraries listed below

• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• openXC7 / toolchain-installer
  Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
  ☆77Updated 11 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• tongchen126 / Boot-Debian-On-Litex-Rocket
  ☆13Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆55Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆81Updated 4 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆57Updated this week
• jeras / rp32
  RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
  ☆15Updated last week
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆59Updated 2 weeks ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆89Updated this week
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 5 months ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆92Updated 4 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• projf / fpgatools
  Tools for FPGA development.
  ☆45Updated 2 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆121Updated 8 years ago
• ldoolitt / vhd2vl
  ☆132Updated 5 months ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 9 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆63Updated last week
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆50Updated 2 years ago
• olofk / qerv
  ☆16Updated 3 weeks ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆27Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year