amstan / qoi-fpga
Quite OK Image FPGA Encoder and Decoder
☆14Updated last year
Related projects ⓘ
Alternatives and complementary repositories for qoi-fpga
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆18Updated 8 months ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- IceCore Ice40 HX based modular core☆44Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆22Updated 3 years ago
- Miscellaneous ULX3S examples (advanced)☆74Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆48Updated last year
- BlackIceMx - Core Module carrier with MixMods/Pmod interfaces☆16Updated 5 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆32Updated last week
- Power analysis of the ICE40UP5K-SG48 devices☆22Updated 4 years ago
- Board and connector definition files for nMigen☆29Updated 4 years ago
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆22Updated 4 months ago
- Tools for FPGA development.☆44Updated last year
- A wishbone controlled PWM (audio) controller☆15Updated 10 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆18Updated 9 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- EDA Tools: Xilinx ISE 14.7 Dockerfile☆21Updated 2 years ago
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 3 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆59Updated this week
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 7 months ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆60Updated 5 months ago
- SDRAM controller with multiple wishbone slave ports☆28Updated 6 years ago
- Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K☆23Updated 2 years ago
- Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm☆32Updated 6 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆48Updated 3 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆27Updated 5 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆19Updated 2 years ago
- Another size-optimized RISC-V CPU for your consideration.☆47Updated this week