merledu / vaquitaLinks
☆18Updated 3 months ago
Alternatives and similar repositories for vaquita
Users that are interested in vaquita are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆203Updated 2 weeks ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 8 months ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- An overview of TL-Verilog resources and projects☆81Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆215Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated 2 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆59Updated 11 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆71Updated last year
- General Purpose AXI Direct Memory Access☆53Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆49Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- ☆97Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated this week
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆24Updated 6 years ago
- ☆34Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- An energy-efficient RISC-V floating-point compute cluster.☆92Updated this week
- Introductory course into static timing analysis (STA).☆94Updated last week
- ☆12Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆170Updated 8 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆24Updated 6 years ago
- RISC-V Verification Interface☆97Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Complete tutorial code.☆21Updated last year