Alternatives and similar repositories for Open_RegModel:

Users that are interested in Open_RegModel are comparing it to the libraries listed below

• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆36Updated last year
• hjking / uvm_gen
  UVM Generator
  ☆44Updated 10 months ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆46Updated 10 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆54Updated 6 months ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆72Updated 4 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆112Updated 7 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆81Updated 4 months ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆82Updated 3 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆31Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆41Updated 5 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆31Updated 4 years ago
• wudayemen / gen_apb_file
  ☆67Updated 3 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆38Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆99Updated 3 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆43Updated 3 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆38Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆60Updated 4 years ago
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆13Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆139Updated 6 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆37Updated 5 years ago