zhajio1988 / Open_RegModel
Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
☆66Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for Open_RegModel
- UVM Testbench For SystemVerilog Combinator Implementation☆51Updated 7 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- amba3 apb/axi vip☆45Updated 9 years ago
- UVM register utility generation by inputting xls table☆34Updated last year
- Generate UVM register model from compiled SystemRDL input☆51Updated 2 months ago
- UVM Generator☆43Updated 6 months ago
- SystemVerilog VIP for AMBA APB protocol☆67Updated 3 years ago
- UVM AHB VIP☆76Updated 2 years ago
- UART design in SV and verification using UVM and SV☆37Updated 4 years ago
- JSON lib in Systemverilog☆42Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆30Updated 4 years ago
- ☆34Updated 9 years ago
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆29Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- Verification IP for APB protocol☆56Updated 3 years ago
- soc integration script and integration smoke script☆21Updated 2 years ago
- Yet Another Simulation Architecture☆73Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆89Updated 6 years ago
- AXI4 BFM in Verilog☆32Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 8 months ago
- ☆62Updated 3 years ago
- System verilog register model for uvm testbenches.☆18Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- DOULOS Easier UVM Code Generator☆26Updated 7 years ago
- UVM agents☆74Updated 7 years ago