veripool / verilog-perl
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
☆127Updated last year
Alternatives and similar repositories for verilog-perl:
Users that are interested in verilog-perl are comparing it to the libraries listed below
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆92Updated last year
- UVM 1.2 port to Python☆250Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆194Updated last year
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆119Updated last week
- ☆150Updated 2 years ago
- AXI interface modules for Cocotb☆244Updated last year
- AHB3-Lite Interconnect☆85Updated 10 months ago
- An AXI4 crossbar implementation in SystemVerilog☆137Updated last month
- SystemVerilog support in VS Code☆135Updated last month
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated 3 weeks ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆138Updated 6 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆198Updated 4 months ago
- A generic class library in SystemVerilog☆81Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆183Updated 4 years ago
- uvm AXI BFM(bus functional model)☆240Updated 11 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- ☆76Updated 6 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- ☆196Updated 2 weeks ago
- ☆46Updated 8 years ago
- AMBA AXI VIP☆387Updated 8 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆109Updated last year
- ☆63Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆146Updated 4 months ago
- Source code repo for UVM Tutorial for Candy Lovers☆181Updated 7 years ago