this repository is vim cfg for verilog.
☆56Oct 17, 2026Updated 3 weeks ago
Alternatives and similar repositories for gvim_for_verilog
Users that are interested in gvim_for_verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆28May 23, 2026Updated 5 months ago
- A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sit…☆28May 27, 2024Updated 2 years ago
- ☆20Aug 30, 2020Updated 6 years ago
- automatic-verilog based on vimscript☆295Oct 24, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆26Oct 14, 2026Updated 3 weeks ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- ☆18Nov 4, 2024Updated 2 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 10 years ago
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 6 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆27Dec 17, 2019Updated 6 years ago
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 5 years ago
- ☆85Aug 30, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementing a LeNet-5 network to achieve hand-written digital's recognition with pure verilog.☆11Dec 9, 2024Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆249Jul 16, 2023Updated 3 years ago
- Verilog极简教程☆37Apr 7, 2019Updated 7 years ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- ☆49Updated this week
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆14Apr 19, 2022Updated 4 years ago
- A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs☆11Jun 19, 2020Updated 6 years ago
- Tenstorrent reference design (harness) for the Open Chiplet Atlas (OCA) architecture☆23Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆27Oct 25, 2026Updated last week
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆121Jul 2, 2023Updated 3 years ago
- Indoor Positioning System using Bluetooth Low Energy Beacons, Raspberry Pi 3 board, based on RSS Fingerprinting and Neural Network algori…☆12Apr 26, 2022Updated 4 years ago
- A simple implementation about LEGv8 instruction set using Verilog HDL.☆12May 8, 2022Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817☆12Nov 10, 2023Updated 2 years ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- my emacs config☆13Mar 12, 2026Updated 7 months ago
- A GNURadio Out-of-Tree module for Automatic Modulation Classification experimentation☆14Nov 16, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆210Jan 28, 2026Updated 9 months ago
- Texture Tile Converter for Bitmaps☆10Mar 9, 2023Updated 3 years ago
- small tools developed at work☆10Aug 25, 2026Updated 2 months ago
- Generate verilog register file from systemRDL description☆14Feb 9, 2024Updated 2 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 5 years ago
- DPD using RLS Algorithm☆15Aug 5, 2018Updated 8 years ago
- Transforming RIS-Assidted Passive Beamforming from Tedious to Simple: A Relaxation Algorithm for Ricain Channel☆12Nov 10, 2022Updated 3 years ago