this repository is vim cfg for verilog.
☆55Apr 24, 2026Updated last month
Alternatives and similar repositories for gvim_for_verilog
Users that are interested in gvim_for_verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- automatic-verilog based on vimscript☆288Oct 24, 2023Updated 2 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆23Dec 17, 2019Updated 6 years ago
- ☆23Mar 27, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog极简教程☆36Apr 7, 2019Updated 7 years ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆12Apr 19, 2022Updated 4 years ago
- Matlab codes for the paper “Distributed multi-stream beamforming in MIMO multi-relay interference networks,” by C. M. Yetis and R. Y. Cha…☆14Feb 9, 2025Updated last year
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆112Jul 2, 2023Updated 2 years ago
- ☆11Jun 16, 2020Updated 5 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件，并在 ARM＋FPGA 完成项目部署，实现通过摄取图片并通过 ARM＋FPGA 综合部署和加速识别算法，并通过显示驱动，在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- verilog实现systolic array及配套IO☆13Dec 2, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆203Jan 28, 2026Updated 3 months ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- A simple implementation about LEGv8 instruction set using Verilog HDL.☆12May 8, 2022Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆417Oct 13, 2024Updated last year
- DPD using RLS Algorithm☆15Aug 5, 2018Updated 7 years ago
- MATLAB simulation code for dissertation project report☆14Sep 4, 2022Updated 3 years ago
- my emacs config☆13Mar 12, 2026Updated 2 months ago
- A CIC filter implemented in Verilog☆24Sep 7, 2015Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RTL to GDS via Cadence Tools☆17May 17, 2022Updated 4 years ago
- Transforming RIS-Assidted Passive Beamforming from Tedious to Simple: A Relaxation Algorithm for Ricain Channel☆12Nov 10, 2022Updated 3 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 5 years ago
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆18Jan 11, 2023Updated 3 years ago
- ☆20Apr 14, 2025Updated last year
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- ☆20May 12, 2026Updated 2 weeks ago
- study uvm step by step☆11Mar 28, 2019Updated 7 years ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Artifact associated with CHES 2022 paper https://tches.iacr.org/index.php/TCHES/article/view/9817☆12Nov 10, 2023Updated 2 years ago
- ☆11Apr 29, 2022Updated 4 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Reed Solomon Decoder (204,188)☆13Jul 17, 2014Updated 11 years ago
- asynchronous fifo based on verilog☆16Apr 14, 2022Updated 4 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- ☆110Mar 2, 2026Updated 2 months ago