tyxiumud / gvim_for_verilog
this repository is vim cfg for verilog.
☆36Updated last month
Related projects: ⓘ
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆147Updated 6 years ago
- AXI总线连接器☆89Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆168Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆108Updated 3 years ago
- AXI DMA 32 / 64 bits☆95Updated 10 years ago
- automatic-verilog based on vimscript☆233Updated 10 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 5 years ago
- 数字IC秋招项目、手撕代码☆33Updated 4 months ago
- ☆60Updated 3 years ago
- AXI协议规范中文翻译版☆124Updated 2 years ago
- 我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆62Updated 2 years ago
- commit rtl and build cosim env☆35Updated 5 months ago
- ARM中通过APB总线连接的UART模块☆57Updated 4 years ago
- AMBA bus lecture material☆365Updated 4 years ago
- Some useful documents of Synopsys☆41Updated 2 years ago
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆47Updated 8 years ago
- UVM AHB VIP☆75Updated 2 years ago
- ☆51Updated 8 years ago
- This is the main repository for all the examples for the book Practical UVM☆165Updated 3 years ago
- VIP for AXI Protocol☆100Updated 2 years ago
- ahb scram controller, design and verification☆25Updated 6 years ago
- IC Verification & SV Demo☆42Updated 2 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆102Updated 6 years ago
- ☆133Updated last month
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆90Updated 6 years ago
- UVM examples and projects☆119Updated 5 years ago
- uvm AXI BFM(bus functional model)☆227Updated 11 years ago
- upgrade to e203 (a risc-v core)☆36Updated 4 years ago
- Awesome ASIC design verification☆244Updated 2 years ago