tyxiumud / gvim_for_verilog
this repository is vim cfg for verilog.
☆43Updated 5 months ago
Alternatives and similar repositories for gvim_for_verilog:
Users that are interested in gvim_for_verilog are comparing it to the libraries listed below
- AXI总线连接器☆93Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆180Updated last year
- AXI DMA 32 / 64 bits☆103Updated 10 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆160Updated 6 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆115Updated 3 years ago
- AXI协议规范中文翻译版☆137Updated 2 years ago
- automatic-verilog based on vimscript☆248Updated last year
- 数字IC秋招项目、手撕代码☆33Updated 8 months ago
- Some useful documents of Synopsys☆57Updated 3 years ago
- VIP for AXI Protocol☆120Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- AMBA bus lecture material☆397Updated 4 years ago
- ☆65Updated 3 years ago
- uvm AXI BFM(bus functional model)☆236Updated 11 years ago
- UVM AHB VIP☆78Updated last month
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆108Updated 7 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆75Updated 3 years ago
- ☆19Updated last year
- ahb scram controller, design and verification☆27Updated 6 years ago
- ARM中通过APB总线连接的UART模块☆60Updated 4 years ago
- UVM examples and projects☆124Updated 6 years ago
- This is the main repository for all the examples for the book Practical UVM☆178Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- CPU Design Based on RISCV ISA☆83Updated 7 months ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆134Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆130Updated last month
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆132Updated 2 months ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆193Updated last year