Alternatives and similar repositories for gvim_for_verilog:

Users that are interested in gvim_for_verilog are comparing it to the libraries listed below

• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆34Updated 10 months ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆116Updated 3 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆163Updated 6 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆106Updated 10 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆186Updated last year
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆77Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆110Updated 7 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆250Updated last year
• wudayemen / gen_apb_file
  ☆66Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆49Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• ForrestBlue / cortexm0ds
  ☆57Updated 9 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆80Updated 2 months ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆57Updated last year
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆145Updated 4 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆62Updated 3 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆122Updated 2 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆62Updated 6 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆53Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆182Updated 4 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆60Updated 5 years ago
• wyvernSemi / eccExamples
  Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
  ☆11Updated last year
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆47Updated 3 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆403Updated 5 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆96Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆125Updated 6 years ago