Alternatives and similar repositories for gen_apb_file

Users that are interested in gen_apb_file are comparing it to the libraries listed below

• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆97Updated 2 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆237Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆92Updated 4 months ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆117Updated 8 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆160Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆215Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆109Updated last year
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆34Updated 5 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆149Updated 4 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆190Updated 7 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆135Updated 8 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆51Updated 4 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆160Updated 5 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆78Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆73Updated 6 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆49Updated 2 years ago
• freecores / apbi2c
  APB to I2C
  ☆43Updated 11 years ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆51Updated 11 months ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆35Updated 9 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• ForrestBlue / cortexm0ds
  ☆74Updated 10 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆58Updated 11 years ago
• hjking / uvm_gen
  UVM Generator
  ☆50Updated last year
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆58Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆75Updated 5 years ago