Tian-Changsong / Verilog-AutomaticLinks
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
☆37Updated 12 years ago
Alternatives and similar repositories for Verilog-Automatic
Users that are interested in Verilog-Automatic are comparing it to the libraries listed below
Sorting:
- soc integration script and integration smoke script☆24Updated 3 years ago
- ☆75Updated 4 years ago
- ☆38Updated 10 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆73Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆81Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆100Updated last year
- UVM candy lover testbench which uses YASA as simulation script☆17Updated 5 years ago
- Cortex M0 based SoC☆76Updated 4 years ago
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆22Updated 2 years ago
- ☆34Updated 6 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- APB to I2C☆43Updated 11 years ago
- A simple UVM example with DPI☆45Updated 8 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- UVM register utility generation by inputting xls table☆39Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆32Updated 11 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- ☆80Updated 3 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆11Updated 2 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆48Updated 9 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- Yet Another Simulation Architecture☆79Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆32Updated 5 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago