Alternatives and similar repositories for Verilog-Automatic:

Users that are interested in Verilog-Automatic are comparing it to the libraries listed below

• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆48Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆66Updated 5 years ago
• zhouzaixin / arm_soc
  ☆14Updated 5 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆77Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆53Updated 4 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆20Updated 2 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆85Updated 5 months ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆32Updated this week
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆41Updated 4 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆37Updated 12 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆29Updated 2 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆66Updated 7 months ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆39Updated last year
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆35Updated 5 years ago
• vim-scripts / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆17Updated 2 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• nelsoncsc / easyUVM
  A simple UVM example with DPI
  ☆37Updated 7 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆45Updated 9 years ago
• zion-group / VerilogCodingStyle
  ☆60Updated 4 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago