Tian-Changsong / Verilog-AutomaticLinks
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
☆37Updated 12 years ago
Alternatives and similar repositories for Verilog-Automatic
Users that are interested in Verilog-Automatic are comparing it to the libraries listed below
Sorting:
- UVM candy lover testbench which uses YASA as simulation script☆17Updated 5 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- ☆38Updated 10 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Updated 7 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- ☆75Updated 4 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆73Updated 6 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆99Updated last year
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆81Updated 5 years ago
- A simple UVM example with DPI☆45Updated 8 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆22Updated 2 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- APB to I2C☆43Updated 11 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- ☆33Updated 6 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- UVM examples☆13Updated 10 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 13 years ago
- amba3 apb/axi vip☆52Updated 10 years ago
- Verification IP for I2C protocol☆51Updated 4 years ago
- Yet Another Simulation Architecture☆78Updated 5 years ago