Tian-Changsong / Verilog-AutomaticLinks
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
☆37Updated 12 years ago
Alternatives and similar repositories for Verilog-Automatic
Users that are interested in Verilog-Automatic are comparing it to the libraries listed below
Sorting:
- soc integration script and integration smoke script☆23Updated 2 years ago
- ☆36Updated 10 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆72Updated 4 years ago
- This is a code repo for previous projects in Digital Design & Verification☆17Updated 10 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆19Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆81Updated 4 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- uvm auto generator☆23Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆96Updated last year
- Cortex M0 based SoC☆74Updated 3 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆38Updated 3 years ago
- ☆14Updated 6 years ago
- This is the repository for the IEEE version of the book☆68Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- ☆41Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 8 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- ☆26Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago