Alternatives and similar repositories for bfat

Users that are interested in bfat are comparing it to the libraries listed below

• AsFigo / svck
  ☆14Updated 4 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆55Updated 3 months ago
• growly / bfg
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆11Updated 2 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 5 months ago
• pulp-platform / svase
  ☆32Updated 9 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆47Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆46Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 6 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated last week
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆25Updated this week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• snishizawa / libretto
  Characterizer
  ☆30Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆28Updated 3 weeks ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆36Updated 2 months ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensour…
  ☆17Updated last month
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last week
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆17Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 4 months ago
• pulp-platform / cheshire-ihp130-o
  ☆54Updated 6 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago