Alternatives and similar repositories for bfat

Users that are interested in bfat are comparing it to the libraries listed below

• AsFigo / svck
  ☆14Updated 7 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last month
• pulp-platform / svase
  ☆33Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• growly / bfg
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆13Updated last week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 11 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• Silimate / prunefl
  SystemVerilog file list pruner
  ☆16Updated last month
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆30Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆52Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆12Updated 2 weeks ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• ieee-ceda-datc / datc-rdf-calibrations
  ☆19Updated last year
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆23Updated 9 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆31Updated last year
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago