Alternatives and similar repositories for bfat

Users that are interested in bfat are comparing it to the libraries listed below

• AsFigo / svck
  ☆14Updated 3 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆54Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 4 months ago
• growly / bfg
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆11Updated this week
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆10Updated 3 months ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 5 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 7 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated 2 weeks ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆45Updated 7 months ago
• snishizawa / libretto
  Characterizer
  ☆30Updated last month
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆37Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆43Updated this week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆24Updated last week
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆49Updated this week
• heyfey / sv-pathfinder
  VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…
  ☆24Updated 2 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆44Updated 6 months ago
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆24Updated this week
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆65Updated last week