Alternatives and similar repositories for ofs-agx7-pcie-attach

Users that are interested in ofs-agx7-pcie-attach are comparing it to the libraries listed below

• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• amiq-consulting / physical_coding_library
  ☆18Updated 9 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆113Updated last week
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated 6 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated 3 months ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated last month
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆69Updated 2 weeks ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 9 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated last week
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆16Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated 3 weeks ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆72Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆111Updated 3 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆60Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆110Updated 4 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 9 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆19Updated 6 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆44Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆156Updated 2 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆41Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆65Updated last week
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆177Updated 2 weeks ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆20Updated 9 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• MicrochipTech / Libero-SoC-Design-Suite-Tcl-Examples
  Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.
  ☆10Updated last year
• Lampro-Mellon / Chisel-Training
  ☆25Updated 4 years ago