Alternatives and similar repositories for PulseRain_FP51_MCU:

Users that are interested in PulseRain_FP51_MCU are comparing it to the libraries listed below

• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆42Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆32Updated 3 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆38Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• Postlast / USB-Blaster_STM32f1
  The program for USB-Blaster Chinese version on STM32 works with
  ☆31Updated 7 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆21Updated 10 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• rbarzic / arty-cm0-designstart
  A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
  ☆12Updated 6 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆28Updated 8 years ago
• kazkojima / pdmmic-example
  A simple PDM microphone interface on FPGA
  ☆11Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• AnlogicInfo / anlogic-usbjtag
  A far more light version anlogic-jtag cable with some enhanced functions.
  ☆48Updated 7 months ago
• mnentwig / busbridge3
  Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency
  ☆18Updated 5 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 11 years ago
• gtortone / esp-xvcd
  ESP8266 Xilinx Virtual Cable - wifi JTAG
  ☆39Updated 3 years ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• dukelec / cdpga
  FPGA core boards / evaluation boards based on CDCTL hardware
  ☆91Updated 3 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated 10 months ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆60Updated 9 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• pablomarx / rodinia
  AGM bitstream utilities and decoded files from Supra
  ☆42Updated last year
• skristiansson / i2s
  i2s core, with support for both transmit and receive
  ☆29Updated 6 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 2 months ago
• wuhanstudio / picorv32_tang
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆28Updated last year