j1s1e1 / VerilogPolarCodesLinks
Polar coding, decoding, and testing
☆13Updated 2 years ago
Alternatives and similar repositories for VerilogPolarCodes
Users that are interested in VerilogPolarCodes are comparing it to the libraries listed below
Sorting:
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆53Updated 8 years ago
- Polar Codes Implementation on Vhdl☆15Updated 9 years ago
- NMS_decode☆15Updated 5 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆78Updated 2 years ago
- 最小和算法实现☆10Updated 5 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆47Updated 7 years ago
- Wi-Fi LDPC codec Verilog IP core☆18Updated 6 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆127Updated last month
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆28Updated 5 years ago
- Verilog based BCH encoder/decoder☆130Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆72Updated last month
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 6 years ago
- Hardware Viterbi Decoder in verilog☆28Updated 6 years ago
- Low Density Parity Check Decoder☆18Updated 9 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆31Updated 2 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Updated 5 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆59Updated 2 years ago
- DVB-S2 LDPC Decoder☆28Updated 11 years ago
- this repository is vim cfg for verilog.☆54Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- Learn UVM by small projects☆16Updated 4 years ago
- IEEE 802.11 OFDM-based transceiver system☆41Updated 8 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- verilog☆21Updated 2 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago