Alternatives and similar repositories for PolarDecoder

Users that are interested in PolarDecoder are comparing it to the libraries listed below

• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆50Updated 11 months ago
• Hyacinth2333 / QC_LDPC-ECC
  NMS_decode
  ☆15Updated 5 years ago
• freedomhust / LDPC_MS
  最小和算法实现
  ☆10Updated 5 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆452Updated 5 years ago
• HHHUUUGGGOOO / 2022_CVSD_Final
  Polar Decoder
  ☆11Updated 2 years ago
• biren15 / Design-and-Verification-of-LDPC-Decoder
  - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …
  ☆51Updated 7 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆411Updated last year
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆219Updated 7 years ago
• ziruizhu / ofdm
  Toy OFDM Communication System with FPGA
  ☆12Updated 3 years ago
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆10Updated 5 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆251Updated 12 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆209Updated 2 years ago
• wyvernSemi / eccExamples
  Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
  ☆11Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆356Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆174Updated 7 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆121Updated 7 years ago
• reglin2000 / NCTU-ICLAB-2021-FALL
  ☆12Updated 3 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆559Updated 3 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆315Updated 3 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆266Updated last year
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆202Updated last year
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆123Updated 6 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆274Updated last year
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆140Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆101Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆115Updated 11 years ago
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆41Updated 2 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆93Updated 3 years ago