HHHUUUGGGOOO / 2022_CVSD_FinalLinks
Polar Decoder
☆10Updated 2 years ago
Alternatives and similar repositories for 2022_CVSD_Final
Users that are interested in 2022_CVSD_Final are comparing it to the libraries listed below
Sorting:
- 数字IC秋招项目、手撕代码☆35Updated last year
- this repository is vim cfg for verilog.☆48Updated 10 months ago
- VIP for AXI Protocol☆136Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆126Updated 4 years ago
- Some useful documents of Synopsys☆73Updated 3 years ago
- AXI总线连接器☆97Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆86Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆172Updated 6 years ago
- ☆11Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆119Updated 7 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆103Updated 5 months ago
- Pipeline FFT Implementation in Verilog HDL☆119Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- ☆70Updated 4 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- ☆22Updated last year
- FFT generator using Chisel☆59Updated 3 years ago
- UVM examples and projects☆137Updated 6 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆11Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- IC-contest 2012~2024☆17Updated last year
- UVM AHB VIP☆85Updated 6 months ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆142Updated 6 years ago
- UVM and System Verilog Manuals☆42Updated 6 years ago
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- uvm AXI BFM(bus functional model)☆247Updated 11 years ago