OpenAutomationTechnologies / VHDL_IP-CoresLinks
☆18Updated 5 years ago
Alternatives and similar repositories for VHDL_IP-Cores
Users that are interested in VHDL_IP-Cores are comparing it to the libraries listed below
Sorting:
- VHDL PCIe Transceiver☆32Updated 5 years ago
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated this week
- USB Full Speed PHY☆48Updated 5 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Updated 2 months ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆14Updated 7 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- an sata controller using smallest resource.☆17Updated 12 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- FPGA board-level debugging and reverse-engineering tool☆39Updated 2 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- UART to AXI Stream interface written in VHDL☆18Updated 3 years ago
- USB capture IP☆25Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆29Updated 9 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 3 months ago
- Wishbone controlled I2C controllers☆57Updated last year
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 12 years ago
- general-cores☆21Updated 6 months ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 10 years ago
- ULPI Link Wrapper (USB Phy Interface)☆34Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Small footprint and configurable JESD204B core☆50Updated 3 weeks ago
- ☆20Updated 3 years ago
- DVI to LVDS Verilog converter☆25Updated 9 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33Updated 5 years ago
- Altium PCB project for the Titan PCI Express development card. This card uses the Lattice ECP5 FPGA.☆21Updated 10 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 5 years ago