Alternatives and similar repositories for VHDL_IP-Cores

Users that are interested in VHDL_IP-Cores are comparing it to the libraries listed below

• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• codeshaa / 16-bit-HDLC-using-VHDL
  High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
  ☆29Updated 9 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆36Updated 5 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆13Updated 7 years ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆24Updated 5 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆27Updated last month
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 3 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 weeks ago
• lnls-dig / general-cores
  general-cores
  ☆21Updated 6 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆32Updated 5 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆35Updated last year
• BerkeleyLab / Marble-Mini
  "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE
  ☆22Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 7 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆24Updated 10 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• mnentwig / busbridge3
  Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency
  ☆20Updated 6 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆39Updated 2 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆18Updated 3 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆14Updated last week
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 7 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆31Updated 4 years ago
• linuxbest / ahci_mpi
  an sata controller using smallest resource.
  ☆17Updated 11 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆57Updated last year
• benreynwar / fpga-sdrlib
  Verilog modules for software-defined radio.
  ☆18Updated 13 years ago