Imiloin / PacGocLinks
PC-side code for PacGoc, enterprise grand prize-winning work at PangoMirco Cup CICC 2024. [第八届集创赛紫光同创杯企业大奖获奖作品]
☆17Updated last year
Alternatives and similar repositories for PacGoc
Users that are interested in PacGoc are comparing it to the libraries listed below
Sorting:
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆62Updated 2 years ago
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Updated last year
- fpga跑sobel识别算法☆44Updated 4 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆35Updated last year
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- Step by step tutorial for building CortexM0 SoC☆39Updated 3 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆81Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- FPGA实现简单的图像处理算法☆66Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆218Updated 2 months ago
- AXI总线连接器☆105Updated 5 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board☆33Updated 4 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆39Updated 3 years ago
- ☆83Updated last week
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆139Updated 2 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆67Updated last year
- 2023集创赛紫光同创杯一等奖项目☆142Updated 2 years ago
- ☆38Updated 10 years ago
- ARM中通过APB总线连接的UART模块☆70Updated 5 years ago
- fpga读取摄像头数据上传到上位机,720P@60Hz☆19Updated 4 years ago
- FPGA 同步FIFO与异步FIFO☆32Updated 6 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆50Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆84Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago