briansune / PYNQ-2.7-MNISTLinks
PYNQ-Based MNIST with Tensorflow Lite
☆21Updated 4 months ago
Alternatives and similar repositories for PYNQ-2.7-MNIST
Users that are interested in PYNQ-2.7-MNIST are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 6 months ago
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 11 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- ☆113Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- ☆46Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆46Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Updated 4 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆217Updated 2 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 4 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆156Updated 2 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆56Updated 4 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆19Updated 11 months ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- ☆90Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year