qixingzhang / SummerSchool2022-Vitis-AI

Related projects: ⓘ

• ignperez-udec / MobileNet-V2-inference-HLS
  Codes to implement MobileNet V2 in a FPGA
  ☆22Updated 3 years ago
• Memory-bread / SSD_IN_PYNQ
  a project build the SSD net in pynq-z2
  ☆14Updated 4 years ago
• Maxwellhyh / AMD_AECG_Summer_School_Projects
  ☆16Updated 2 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆109Updated 3 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated last year
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆96Updated 2 years ago
• vivian13maker / The-advanced-work-of-Object-detection-based-on-FPGAs
  ☆21Updated 3 years ago
• matsuda-slab / YOLO_ZYNQ_MASTER
  Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA
  ☆25Updated 2 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆20Updated 2 years ago
• jgoeders / dac_sdc_2022_designs
  ☆16Updated last year
• CHNLeo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆60Updated last year
• xbdxwyh / yolov3_fpga_project
  ☆44Updated last year
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 2 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆16Updated 4 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆43Updated 4 years ago
• AiArtisan / dac_sdc_2022_champion
  ☆20Updated last year
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆74Updated 5 years ago
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆12Updated last week
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆28Updated last month
• clancylea / pynq-sobel
  A demo for accelerating sobel in xilinx's fpga pynq
  ☆17Updated last year
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆36Updated 5 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆47Updated 6 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• hisrg / Neural-Network-Compression-and-Accelerator-on-Hardware
  My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …
  ☆41Updated last year
• Stuart0l / BNN
  HLS code for a BNN accelerator
  ☆15Updated 6 years ago
• a2824256 / HLS-LeNet
  The CNN based on the Xilinx Vivado HLS
  ☆35Updated 2 years ago
• Microdent / Handwritten_Mathematical_Calculator_on_FPGA
  A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.
  ☆34Updated 4 years ago
• GeneralZDS / FPGA-DCNN-Accelerator
  基于HLS的高效深度卷积神经网络FPGA实现方法
  ☆64Updated 5 years ago
• xliu0709 / DACSDC2021
  ☆11Updated 5 months ago
• sefaburakokcu / finn-quantized-yolo
  Low-Precision YOLO on PYNQ with FINN
  ☆26Updated 9 months ago