xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆69Updated 6 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- HLS-based Graph Processing Framework on FPGAs☆150Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆168Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆176Updated 3 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 5 months ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An integrated CGRA design framework☆91Updated 8 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated last year
- Vitis HLS Library for FINN☆210Updated 2 months ago
- ☆71Updated 6 years ago
- view at https://xupsh.github.io/ccc2021/☆23Updated 3 years ago
- ☆38Updated 8 months ago
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆60Updated 4 years ago
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆204Updated 4 years ago
- AMD University Program HLS tutorial☆120Updated last year
- ☆72Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆145Updated 2 weeks ago
- ☆63Updated 5 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆108Updated 7 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago