Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below

• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆68Updated 6 years ago
• Xtra-Computing / ThunderGP
  HLS-based Graph Processing Framework on FPGAs
  ☆149Updated 2 years ago
• groupsada / DeepBurning
  Automatic generation of FPGA-based learning accelerators for the neural network family
  ☆67Updated 5 years ago
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆117Updated 3 months ago
• tuna / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.
  ☆174Updated last month
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆167Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆81Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• maomran / softmax
  Verilog implementation of Softmax function
  ☆70Updated 3 years ago
• awai54st / LUTNet
  ☆60Updated 5 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆46Updated 10 months ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆125Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆59Updated last year
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆201Updated 5 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated this week
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆201Updated 3 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆110Updated 11 months ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• xupsh / ccc2021
  view at https://xupsh.github.io/ccc2021/
  ☆23Updated 3 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆81Updated 6 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• lana555 / dynamatic
  ☆87Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago