Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS:

Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below

• xupsh / ccc2021
  view at https://xupsh.github.io/ccc2021/
  ☆24Updated 2 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 6 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆85Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated 10 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆191Updated 2 weeks ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆147Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆29Updated 4 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆89Updated 6 months ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆60Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last week
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆94Updated 4 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
  ☆165Updated last year
• sharc-lab / FPGA_ECE8893
  ☆33Updated this week
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆144Updated 5 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• RC4ML / Shuhai
  Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…
  ☆106Updated last year
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆132Updated this week
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆71Updated 10 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 9 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 3 years ago
• chenhaoc / cnnhwpe
  ☆65Updated 2 years ago
• a2824256 / HLS-LeNet
  The CNN based on the Xilinx Vivado HLS
  ☆37Updated 3 years ago