Xilinx / PYNQ_PeripheralsLinks
☆24Updated 4 years ago
Alternatives and similar repositories for PYNQ_Peripherals
Users that are interested in PYNQ_Peripherals are comparing it to the libraries listed below
Sorting:
- PYNQ Composabe Overlays☆74Updated last year
- ☆72Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- DPU on PYNQ☆241Updated 5 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- AMD University Program HLS tutorial☆123Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 2 weeks ago
- ☆104Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- IC implementation of TPU☆147Updated 6 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆76Updated 5 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆170Updated 2 years ago
- A collection of tutorials for the fpgaConvNet framework.☆48Updated last year
- ☆54Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- Vitis HLS Library for FINN☆213Updated 3 weeks ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- RISC-V Integration for PYNQ☆180Updated 6 years ago
- ☆40Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆75Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆122Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- Hardware accelerator for convolutional neural networks☆64Updated 3 years ago