Xilinx / PYNQ_PeripheralsLinks
☆22Updated 3 years ago
Alternatives and similar repositories for PYNQ_Peripherals
Users that are interested in PYNQ_Peripherals are comparing it to the libraries listed below
Sorting:
- PYNQ Composabe Overlays☆73Updated last year
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆65Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- ☆58Updated 5 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- ☆52Updated 6 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- Matrix Multiply and Accumulate unit written in System Verilog☆11Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 7 months ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆34Updated 6 years ago