Alternatives and similar repositories for Asynchronous-Fifo

Users that are interested in Asynchronous-Fifo are comparing it to the libraries listed below

• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆133Updated 4 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆482Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆225Updated 2 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆186Updated 7 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆272Updated 2 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 9 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆145Updated 6 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆52Updated last year
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆158Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆209Updated 2 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆232Updated last year
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆39Updated last year
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆13Updated 5 years ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆47Updated 9 months ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆105Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆131Updated 8 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆71Updated 9 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆37Updated 5 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆43Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆56Updated 4 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆392Updated 2 months ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆213Updated 2 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆428Updated last year
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆188Updated 13 years ago