LoveLonelyTime / LLTRISC-VLinks
LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.
☆17Updated last year
Alternatives and similar repositories for LLTRISC-V
Users that are interested in LLTRISC-V are comparing it to the libraries listed below
Sorting:
- ☆64Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆19Updated 2 years ago
- An exquisite superscalar RV32GC processor.☆165Updated last year
- ☆92Updated 4 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- ☆71Updated last week
- ☆90Updated 2 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 4 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆74Updated 3 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- ☆47Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆223Updated this week
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated 2 years ago
- XiangShan Frontend Develop Environment☆68Updated this week
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- Pick your favorite language to verify your chip.☆77Updated last week
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆151Updated last year
- AXI协议规范中文翻译版☆171Updated 3 years ago
- Open source high performance IEEE-754 floating unit☆89Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆194Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago