POETSII / tinselLinks
Manythread RISC-V overlay for FPGA clusters
☆38Updated last week
Alternatives and similar repositories for tinsel
Users that are interested in tinsel are comparing it to the libraries listed below
Sorting:
- A core language for rule-based hardware design 🦑☆160Updated 3 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 6 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆159Updated 2 months ago
- Main page☆128Updated 5 years ago
- Formal specification of RISC-V Instruction Set☆101Updated 5 years ago
- Time-sensitive affine types for predictable hardware generation☆145Updated last week
- Haskell library for hardware description☆104Updated last month
- CHERI-RISC-V model written in Sail☆64Updated 2 months ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- ☆40Updated 4 years ago
- A formal semantics of the RISC-V ISA in Haskell☆170Updated 2 years ago
- A generic test bench written in Bluespec☆55Updated 4 years ago
- Galois RISC-V ISA Formal Tools☆61Updated last month
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆93Updated 2 weeks ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last week
- Verilog development and verification project for HOL4☆27Updated 4 months ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆75Updated 5 years ago
- A RiscV processor implementing the RV32I instruction set written in Clash☆53Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- ☆103Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- ☆26Updated 2 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last month