POETSII / tinselLinks
Manythread RISC-V overlay for FPGA clusters
☆38Updated 2 years ago
Alternatives and similar repositories for tinsel
Users that are interested in tinsel are comparing it to the libraries listed below
Sorting:
- A core language for rule-based hardware design 🦑☆160Updated 2 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆36Updated 5 months ago
- ☆40Updated 3 years ago
- Main page☆128Updated 5 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆158Updated last month
- Time-sensitive affine types for predictable hardware generation☆145Updated this week
- Haskell library for hardware description☆104Updated 2 weeks ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- CHERI-RISC-V model written in Sail☆64Updated last month
- Formal specification of RISC-V Instruction Set☆101Updated 5 years ago
- A generic test bench written in Bluespec☆54Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆93Updated last year
- The source code to the Voss II Hardware Verification Suite☆56Updated last month
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆126Updated 3 years ago
- ☆26Updated 2 years ago
- Chisel/Firrtl execution engine☆153Updated last year
- Galois RISC-V ISA Formal Tools☆61Updated 3 weeks ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 3 months ago
- A formal semantics of the RISC-V ISA in Haskell☆170Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆86Updated 3 weeks ago
- ☆103Updated 3 years ago
- Verilog AST☆21Updated last year
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference☆73Updated 2 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 weeks ago
- Verilog development and verification project for HOL4☆27Updated 4 months ago