tukl-msd / DRAMSpec
A High-Level DRAM Timing, Power and Area Exploration Tool
☆27Updated 4 years ago
Alternatives and similar repositories for DRAMSpec:
Users that are interested in DRAMSpec are comparing it to the libraries listed below
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- ☆27Updated 9 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆62Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- ☆91Updated last year
- cycle accurate Network-on-Chip Simulator☆26Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- gem5 repository to study chiplet-based systems☆68Updated 5 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆42Updated 10 months ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆15Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- Processing in Memory Emulation☆19Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆68Updated 5 years ago
- Heterogeneous simulator for DECADES Project☆32Updated 9 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆85Updated 5 months ago
- ☆22Updated 3 months ago
- A list of our chiplet simulaters☆29Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆47Updated 2 months ago
- Benchmarks for Accelerator Design and Customized Architectures☆118Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated last week
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆16Updated last year
- Project repo for the POSH on-chip network generator☆43Updated last year