CMU-SAFARI / CoMeTLinks
CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper https://arxiv.org/pdf/2402.18769.pdf
☆10Updated last year
Alternatives and similar repositories for CoMeT
Users that are interested in CoMeT are comparing it to the libraries listed below
Sorting:
- ☆15Updated 2 weeks ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- 16 bit serial multiplier in SystemVerilog☆12Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- ☆16Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆14Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- ☆36Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…☆12Updated last year
- ☆13Updated 3 years ago
- ☆25Updated last year
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- ☆27Updated 6 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- Next generation CGRA generator☆115Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆63Updated 6 months ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago
- ☆24Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Public release☆57Updated 6 years ago