CMU-SAFARI / DRAM-Datasheet-SurveyLinks
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
☆11Updated 3 years ago
Alternatives and similar repositories for DRAM-Datasheet-Survey
Users that are interested in DRAM-Datasheet-Survey are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Processing in Memory Emulation☆20Updated 2 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- ☆30Updated 2 months ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- ☆14Updated 2 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 3 years ago
- ☆12Updated 8 months ago
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆83Updated 9 months ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆11Updated last year
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆26Updated last year
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆21Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆30Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆16Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆21Updated 11 months ago
- corundum work on vu13p☆18Updated last year
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆11Updated last year
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year