estwings57 / HMC-MAC
Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
☆11Updated 8 years ago
Alternatives and similar repositories for HMC-MAC:
Users that are interested in HMC-MAC are comparing it to the libraries listed below
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆20Updated 6 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- Graph accelerator on FPGAs and ASICs☆12Updated 6 years ago
- NeuraChip Accelerator Simulator☆11Updated 11 months ago
- ☆16Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆18Updated 11 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆23Updated 3 months ago
- ☆23Updated 4 years ago
- Heterogenous ML accelerator☆18Updated 6 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆49Updated 3 months ago
- ☆13Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated 3 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆34Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 2 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆17Updated 2 years ago
- ☆9Updated 2 years ago
- ☆9Updated 2 months ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆35Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆25Updated 11 months ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago