PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system implemented on an FPGA. Described in our paper: https://arxiv.org/abs/2111.00082
☆72Dec 11, 2023Updated 2 years ago
Alternatives and similar repositories for PiDRAM
Users that are interested in PiDRAM are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆56Jun 12, 2021Updated 4 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Aug 2, 2019Updated 6 years ago
- A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combi…☆182Oct 1, 2022Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆31Oct 23, 2023Updated 2 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Feb 13, 2017Updated 9 years ago
- PIM-ML is a benchmark for training machine learning algorithms on the UPMEM architecture, which is the first publicly-available real-worl…☆25Jan 7, 2025Updated last year
- ☆11Mar 14, 2023Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Processing in Memory Emulation☆23Feb 24, 2023Updated 3 years ago
- ☆22Jun 4, 2023Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆41Mar 1, 2019Updated 7 years ago
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆18Jan 12, 2023Updated 3 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 3 years ago
- CoMeT is a new low-cost RowHammer mitigation that uses Count-Min Sketch-based aggressor row tracking, as described in our HPCA'24 paper h…☆11Jan 23, 2026Updated last month
- DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…☆110Aug 10, 2025Updated 6 months ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆14Feb 2, 2026Updated last month
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆144Aug 24, 2023Updated 2 years ago
- ☆22Feb 18, 2025Updated last year
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆14Sep 15, 2022Updated 3 years ago
- New RowHammer mitigation mechanism that is area-, performance-, and energy-efficient especially at very low (e.g., 125) RowHammer thresho…☆17May 2, 2024Updated last year
- ☆13Jul 11, 2023Updated 2 years ago
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆212Apr 18, 2023Updated 2 years ago
- ☆17Oct 7, 2025Updated 4 months ago
- Processing-In-Memory (PIM) Simulator☆222Dec 12, 2024Updated last year
- PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is dev…☆169Apr 29, 2024Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 5 years ago
- ☆14Feb 18, 2021Updated 5 years ago
- ☆14Mar 10, 2024Updated last year
- ☆14Mar 4, 2015Updated 11 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Nov 23, 2023Updated 2 years ago
- su su su supernova☆25Jan 9, 2025Updated last year
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 8 months ago
- NATSA is the first near-data-processing accelerator for time series analysis based on the Matrix Profile (SCRIMP) algorithm. NATSA exploi…☆16Jun 14, 2023Updated 2 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆451Aug 3, 2024Updated last year
- ☆24Apr 20, 2024Updated last year