SkyworksSolutionsInc / fplibLinks
Fixed point math library for SystemVerilog
☆27Updated 8 months ago
Alternatives and similar repositories for fplib
Users that are interested in fplib are comparing it to the libraries listed below
Sorting:
- Prefix tree adder space exploration library☆57Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- An automatic clock gating utility☆50Updated 3 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- mantle library☆44Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- ☆48Updated 5 months ago
- PicoRV☆44Updated 5 years ago
- Raptor end-to-end FPGA Compiler and GUI☆82Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Xilinx Unisim Library in Verilog☆80Updated 5 years ago
- ☆37Updated 3 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆47Updated 6 months ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Updated 3 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- SpinalHDL Hardware Math Library☆89Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆72Updated this week
- ASIC implementation flow infrastructure☆49Updated this week
- This repository is for (pre-)release versions of the Revolution EDA.☆42Updated last month
- ☆70Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- ☆23Updated 2 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- ☆53Updated last week