Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determined design in a familiar context. The tools used are Icarus verilog and gtkwave.
☆15Jun 15, 2016Updated 9 years ago
Alternatives and similar repositories for NCL_sandbox
Users that are interested in NCL_sandbox are comparing it to the libraries listed below
Sorting:
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated this week
- FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64☆15Aug 22, 2019Updated 6 years ago
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- Minimal GUI in Go initially based on https://github.com/faiface/gui☆11Mar 1, 2020Updated 6 years ago
- Get results from search engines.☆12Nov 21, 2022Updated 3 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 8 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 6 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆44May 12, 2016Updated 9 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- Automatically generate frontends for go programs☆40Apr 15, 2018Updated 7 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆27Jan 21, 2026Updated last month
- Why can't the 6502 virtualize itself? Good question.☆21May 15, 2024Updated last year
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Feb 24, 2026Updated last week
- A simple live-reloading tool for developing HTML.☆31Nov 30, 2024Updated last year
- ☆25Sep 27, 2018Updated 7 years ago
- RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.☆39Jan 5, 2017Updated 9 years ago
- ☆28Nov 15, 2019Updated 6 years ago
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Oct 20, 2019Updated 6 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- Fine Grain FPGA Overlay Architecture and Tools☆27Nov 5, 2021Updated 4 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 4 months ago
- OpenFPGA☆34Mar 12, 2018Updated 7 years ago
- FPGA USB 1.1 Low-Speed Implementation☆35Oct 3, 2018Updated 7 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Apr 2, 2025Updated 11 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 5 years ago
- A guide on how to emulate an NVMe SPDM responder device with QEMU and Linux. Additionally, instructions on setting up and testing the (in…☆11Sep 3, 2024Updated last year
- Forcefully stops the services related to Windows 10 background updates.☆10Jul 18, 2018Updated 7 years ago
- Bootloader tool for OLS☆22Jul 17, 2016Updated 9 years ago
- An application for comparing two binary files☆11Feb 22, 2019Updated 7 years ago
- LDAP Schema for OwnCloud Quota☆10Jun 19, 2018Updated 7 years ago
- Ice40 open source HDMI examples on BlackIce II☆11May 12, 2022Updated 3 years ago
- A hex editor widget for Qt5☆10Feb 8, 2016Updated 10 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 3 months ago
- Generate Go bindings for shared C libraries.☆15Jul 13, 2024Updated last year
- Docker image for squid-deb-proxy☆11Jun 22, 2017Updated 8 years ago
- WWVB emulator using an ESP32☆10Apr 2, 2020Updated 5 years ago
- A new CASPER toolflow based on an HDL primitives library☆17Apr 11, 2012Updated 13 years ago