Alternatives and similar repositories for NCL_sandbox

Users that are interested in NCL_sandbox are comparing it to the libraries listed below

• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated 3 months ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆31Updated 9 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 2 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated 11 months ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 9 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆16Updated this week
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆16Updated 3 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week