Deepak42074 / Sky130-RTL-Design-And-Synthesis-Using-VerilogLinks
☆18Updated 3 years ago
Alternatives and similar repositories for Sky130-RTL-Design-And-Synthesis-Using-Verilog
Users that are interested in Sky130-RTL-Design-And-Synthesis-Using-Verilog are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆143Updated last week
- BlackParrot on Zynq☆47Updated last week
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- ☆43Updated 3 years ago
- This is a tutorial on standard digital design flow☆80Updated 4 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- ☆79Updated 11 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- ☆28Updated 6 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- SRAM☆22Updated 5 years ago
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆75Updated last month
- ☆31Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year