akshararavi / ViT-Malware-Detector
A vision transformer based framework for classifying executable images as benign or malicious
☆10Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for ViT-Malware-Detector
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆9Updated 7 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- opensource EDA tool flor VLSI design☆29Updated last year
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆47Updated 2 weeks ago
- Verilog HDL files☆100Updated 5 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- This repository contains the design files of RISC-V Single Cycle Core☆29Updated 11 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆40Updated last year
- ☆13Updated 2 years ago
- ☆99Updated 10 months ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆16Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆98Updated 2 years ago
- ☆22Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆96Updated 9 months ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆12Updated 4 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆212Updated 3 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- UVM and System Verilog Manuals☆36Updated 5 years ago
- ☆16Updated 10 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆15Updated 6 months ago
- Implementation of RISC-V RV32I☆13Updated 2 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- Architectural design of data router in verilog☆27Updated 4 years ago