akshararavi / ViT-Malware-DetectorLinks
A vision transformer based framework for classifying executable images as benign or malicious
☆9Updated last year
Alternatives and similar repositories for ViT-Malware-Detector
Users that are interested in ViT-Malware-Detector are comparing it to the libraries listed below
Sorting:
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆263Updated 2 months ago
- Verilog HDL files☆147Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆113Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆154Updated 11 months ago
- opensource EDA tool flor VLSI design☆33Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆52Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆78Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆89Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 9 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆29Updated 3 weeks ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 11 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆140Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆51Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆45Updated 4 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆77Updated 2 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- SystemVerilog Tutorial☆160Updated 3 months ago
- ☆15Updated 2 years ago
- An overview of TL-Verilog resources and projects☆80Updated 4 months ago
- ☆41Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆18Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆26Updated last year
- ☆114Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆135Updated 2 months ago
- 100 Days of RTL☆386Updated 11 months ago