akshararavi / ViT-Malware-Detector
A vision transformer based framework for classifying executable images as benign or malicious
☆10Updated last year
Alternatives and similar repositories for ViT-Malware-Detector:
Users that are interested in ViT-Malware-Detector are comparing it to the libraries listed below
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆19Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆110Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 8 months ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆44Updated 9 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- ☆10Updated 2 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 5 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- ☆15Updated 2 years ago
- ☆22Updated last year
- Lecture about FIR filter on an FPGA☆12Updated 11 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆33Updated 3 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆27Updated 11 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆47Updated 2 months ago
- 32 bit RISC-V CPU implementation in Verilog☆27Updated 3 years ago
- ☆12Updated 3 weeks ago
- ☆16Updated 9 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- 6-stage in-order dual-issue superscalar risc-v cpu with floating point unit☆12Updated this week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago