psherman42 / riscv-easy-as-pi
Getting started with RISC-V
☆11Updated last year
Alternatives and similar repositories for riscv-easy-as-pi:
Users that are interested in riscv-easy-as-pi are comparing it to the libraries listed below
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆93Updated last week
- Building and deploying container images for open source electronic design automation (EDA)☆113Updated 6 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆32Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆95Updated last month
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆46Updated 2 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 5 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆73Updated last year
- A pipelined RISC-V processor☆55Updated last year
- ☆24Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 2 weeks ago
- Labs for the Ibex Demo System☆12Updated last year
- Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.☆32Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆35Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆144Updated 5 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- M-extension for RISC-V cores.☆30Updated 5 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆51Updated 3 months ago
- nextpnr portable FPGA place and route tool☆20Updated 8 months ago
- The multi-core cluster of a PULP system.☆89Updated 2 weeks ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆39Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆90Updated 7 months ago
- Raptor end-to-end FPGA Compiler and GUI☆78Updated 4 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆80Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆208Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week