magicYang1573 / llm-hardware-test-generation
☆22Updated 6 months ago
Alternatives and similar repositories for llm-hardware-test-generation:
Users that are interested in llm-hardware-test-generation are comparing it to the libraries listed below
- ☆11Updated 4 months ago
- ☆11Updated last year
- An open-source benchmark for generating design RTL with natural language☆77Updated 2 months ago
- This is a python repo for flattening Verilog☆15Updated last week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆39Updated 4 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆14Updated last year
- Pipelined RISC-V CPU☆22Updated 3 years ago
- An infrastructure for integrated EDA☆38Updated last year
- A hardware synthesis framework with multi-level paradigm☆36Updated last week
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated 10 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 10 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆49Updated 3 years ago
- CGRA framework with vectorization support.☆21Updated this week
- Fast Symbolic Repair of Hardware Design Code☆20Updated this week
- Dataset for ML-guided Accelerator Design☆33Updated 2 months ago
- ☆21Updated 6 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆14Updated 6 months ago
- ☆32Updated 3 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆142Updated 3 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- An integrated CGRA design framework☆85Updated 2 months ago
- ☆36Updated this week
- The open-sourced version of BOOM-Explorer☆36Updated last year
- Project repo for the POSH on-chip network generator☆43Updated last year
- ☆12Updated this week
- Advanced Architecture Labs with CVA6☆54Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 4 months ago
- ☆29Updated last month