magicYang1573 / llm-hardware-test-generationLinks
☆33Updated last year
Alternatives and similar repositories for llm-hardware-test-generation
Users that are interested in llm-hardware-test-generation are comparing it to the libraries listed below
Sorting:
- ☆15Updated last year
- ☆31Updated 8 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆75Updated 8 months ago
- An open-source benchmark for generating design RTL with natural language☆150Updated last year
- ☆53Updated 3 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆53Updated 11 months ago
- This is a python repo for flattening Verilog☆20Updated 7 months ago
- This is a repo to store circuit design datasets☆19Updated last year
- ☆51Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆68Updated 4 months ago
- ☆41Updated last year
- ☆20Updated 3 years ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆240Updated 10 months ago
- Fix syntax errors of LLM-generated RTL☆39Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆27Updated last year
- ☆33Updated 8 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆30Updated 5 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆29Updated 8 months ago
- Pick your favorite language to verify your chip.☆73Updated last week
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆26Updated 7 months ago
- ☆52Updated 10 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- An infrastructure for integrated EDA☆42Updated 2 years ago
- ☆192Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- ☆13Updated 2 years ago