Subhasis-Sahu / SFAL-VSDLinks
☆13Updated last year
Alternatives and similar repositories for SFAL-VSD
Users that are interested in SFAL-VSD are comparing it to the libraries listed below
Sorting:
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- This repo provide an index of VLSI content creators and their materials☆161Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆29Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆122Updated 3 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆278Updated 6 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- 100 Days of RTL☆402Updated last year
- ☆117Updated last year
- opensource EDA tool flor VLSI design☆35Updated 2 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆26Updated 10 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆23Updated 5 months ago
- ☆17Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆165Updated last year
- ☆15Updated 2 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆432Updated 4 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆20Updated 4 years ago
- RTL to GDS via Cadence Tools☆15Updated 3 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- SystemVerilog Tutorial☆185Updated last week
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆17Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated 4 months ago
- Verilog HDL files☆161Updated last year
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Updated 2 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆31Updated last year
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆51Updated last year
- ☆22Updated 2 years ago
- ☆17Updated last year