Alternatives and similar repositories for SFAL-VSD:

Users that are interested in SFAL-VSD are comparing it to the libraries listed below

• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆19Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 8 months ago
• arunkpv / vsd-hdp
  ☆16Updated 10 months ago
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆23Updated 11 months ago
• mehwish411 / 5-Staged-Pipelined-RISC-V-32I-Processor
  5 stage pipeline implementation of RISC-V 32I Processor.
  ☆10Updated 5 months ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆30Updated 5 years ago
• Akash-Perla / ASIC-Design
  This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)
  ☆12Updated 5 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆149Updated 8 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆57Updated 2 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆32Updated last year
• Devipriya1921 / VSDBabySoC_ICC2
  ☆10Updated 2 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆110Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆142Updated this week
• Artityagi123456789 / 100DaysofRTL
  ☆16Updated last year
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆11Updated 10 months ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆57Updated last year
• maazm007 / vsdsquadron-mini-internship
  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
  ☆27Updated last year
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆110Updated 2 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆76Updated last year
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• ItzzInfinity / 100-days-of-RTL
  Trying to get a new skill
  ☆23Updated 4 months ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆71Updated 2 years ago
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆13Updated 3 years ago
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year