VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
☆33Jul 21, 2025Updated last year
Alternatives and similar repositories for vsdsquadron-mini-internship
Users that are interested in vsdsquadron-mini-internship are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of RISC-V RV32I☆32Aug 30, 2022Updated 3 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- ☆14Sep 29, 2024Updated last year
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆15Aug 25, 2025Updated 11 months ago
- DMA Project using Verilog HDL☆14Dec 26, 2019Updated 6 years ago
- Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim☆14May 8, 2021Updated 5 years ago
- I have implemented a fake note detection unit with image processing algorithms in MATLAB. The aspect ratio is calculated initially for th…☆11Sep 18, 2023Updated 2 years ago
- This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the A…☆16Sep 9, 2025Updated 10 months ago
- ☆49Apr 7, 2024Updated 2 years ago
- ☆18Sep 16, 2022Updated 3 years ago
- RV64IMAC modelling using System Verilog HDL☆26Aug 10, 2024Updated last year
- ☆45Jul 20, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆20Aug 19, 2024Updated last year
- This project is all about the quest of building a platooning capable robot.☆15Mar 2, 2020Updated 6 years ago
- ☆25Nov 11, 2025Updated 8 months ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆72Apr 13, 2024Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- Repository containing code for my learning of classical and quantum machine learning. Includes a variational quantum classifier, fully-co…☆12Nov 2, 2021Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Arduino library for radio-controlled models using the CRSF protocol☆25Mar 12, 2025Updated last year
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 10 months ago
- ☆17Feb 16, 2023Updated 3 years ago
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- ☆13Jan 1, 2023Updated 3 years ago
- Scratchpad repository for the 100-day FPGA challenge☆14Jul 11, 2019Updated 7 years ago
- The purpose of our project is to develop a system that can automatically detect cancer from the blood cell images. This system uses a con…☆22Jun 12, 2021Updated 5 years ago
- Scripts for aligning cryo-electron microscopy direct electron detector movies on whole movies or individual particle trajectories☆12Mar 28, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Submission repo for Coderspree☆21Jul 10, 2022Updated 4 years ago
- ☆16Oct 14, 2024Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆85Dec 14, 2023Updated 2 years ago
- Dr Sparsh's lecture slides on RISC-V ISA☆22Jun 9, 2025Updated last year
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Semiconductor Packaging Fundamentals☆36May 19, 2025Updated last year