rajdeep66 / edaBundle_whyRD
opensource EDA tool flor VLSI design
☆31Updated last year
Alternatives and similar repositories for edaBundle_whyRD:
Users that are interested in edaBundle_whyRD are comparing it to the libraries listed below
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆104Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆107Updated last year
- This repo provide an index of VLSI content creators and their materials☆140Updated 5 months ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- ☆14Updated 11 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆22Updated 7 months ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- ☆16Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆63Updated last year
- ☆9Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆14Updated 9 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆12Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆13Updated last year
- ☆22Updated last year
- ☆40Updated last year
- Verilog HDL files☆118Updated 8 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆23Updated 8 months ago
- ☆15Updated 6 months ago
- ☆11Updated this week
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 5 months ago
- ☆14Updated 11 months ago
- ☆16Updated last year
- ☆16Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆101Updated last year
- SystemVerilog Tutorial☆121Updated this week
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆62Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆69Updated 2 years ago