Alternatives and similar repositories for xup_fpga_vivado_flow

Users that are interested in xup_fpga_vivado_flow are comparing it to the libraries listed below

• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated 7 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆70Updated last month
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆179Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated last week
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆47Updated last year
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 9 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 10 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆87Updated 5 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 3 months ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆86Updated 2 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆227Updated 2 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆68Updated this week
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 4 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• Xilinx / xup_embedded_system_design_flow
  AMD Xilinx University Program Embedded tutorial
  ☆38Updated 2 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆107Updated last week
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated last month
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆61Updated 2 years ago