Alternatives and similar repositories for xup_fpga_vivado_flow

Users that are interested in xup_fpga_vivado_flow are comparing it to the libraries listed below

• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated last week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆72Updated 3 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆75Updated 4 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last week
• opensmartnic / cocotb_primer
  understanding of cocotb （In Chinese Only）
  ☆20Updated 6 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆79Updated 11 years ago
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆56Updated 5 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆85Updated 2 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆55Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago
• oprecomp / DDR4_controller
  ☆70Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆60Updated last week
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆44Updated 8 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆67Updated 9 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆78Updated 7 years ago
• Xilinx / xup_embedded_system_design_flow
  AMD Xilinx University Program Embedded tutorial
  ☆42Updated 2 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆185Updated 3 weeks ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆162Updated 3 years ago