ShekharShwetank / Quantized_Neural_Network_on_RISC-VLinks
Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) QSPI Flash | 4-stage pipeline
☆13Updated 4 months ago
Alternatives and similar repositories for Quantized_Neural_Network_on_RISC-V
Users that are interested in Quantized_Neural_Network_on_RISC-V are comparing it to the libraries listed below
Sorting:
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Updated last year
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆31Updated 6 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆30Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆124Updated 3 years ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆290Updated 8 months ago
- ☆13Updated last year
- VHDL course at Brno University of Technology☆128Updated last week
- This repo provide an index of VLSI content creators and their materials☆164Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆20Updated last year
- ☆18Updated 2 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆153Updated 3 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆106Updated 2 years ago
- LLM-Aided FPGA Design and Debug Flow☆23Updated 5 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Updated 2 years ago
- 100 Days of RTL☆407Updated last year
- ☆22Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated 2 years ago
- Verilog HDL files☆170Updated last year
- ☆47Updated last year
- ☆44Updated 2 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆16Updated 3 months ago
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆25Updated 10 months ago
- Trying to get a new skill☆31Updated last year
- VHDL Guide☆75Updated 4 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Updated last year
- ☆116Updated 2 years ago