Dual-Core Out-of-Order MIPS CPU Design
☆22May 8, 2025Updated last year
Alternatives and similar repositories for 437_OoO
Users that are interested in 437_OoO are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated 2 months ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Software and resources to help Purdue students (and others) continue developing with SystemVerilog after losing access to proprietary too…☆17Jun 13, 2021Updated 4 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆12Aug 26, 2016Updated 9 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- ☆40Oct 21, 2025Updated 6 months ago
- Advanced Architecture Labs with CVA6☆82Jan 16, 2024Updated 2 years ago
- Public Lab Documents for ECE 36200☆34Apr 16, 2026Updated 3 weeks ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆23Jan 24, 2026Updated 3 months ago
- design and verification of asynchronous circuits☆50Apr 26, 2026Updated last week
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Generating Efficient AI-Centric Kernels☆93Updated this week
- Unofficial terminal application for the University of Alicante library written in C++☆10Mar 26, 2020Updated 6 years ago
- Contains commonly used UVM components (agents, environments and tests).☆33Aug 17, 2018Updated 7 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 6 months ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Jan 15, 2018Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs☆17Mar 6, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆12Jan 11, 2024Updated 2 years ago
- 🖌 Style Guidelines for opsdroid☆10May 15, 2023Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- RTL data structure☆66Apr 23, 2026Updated 2 weeks ago
- Inkscape extension to export selected objects to cetz (Typst) format☆18Jan 17, 2025Updated last year
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RTLMeter benchmark suite☆31May 1, 2026Updated last week
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆30Feb 21, 2024Updated 2 years ago
- ☆18Jul 3, 2025Updated 10 months ago
- C Firmware for FHNW P5 DSP Board based on STM32F412 / TLV320aic☆12Jan 15, 2020Updated 6 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago