accellera-official / cciLinks
SystemC Configuration, Control and Inspection (CCI)
☆19Updated 2 weeks ago
Alternatives and similar repositories for cci
Users that are interested in cci are comparing it to the libraries listed below
Sorting:
- SystemC Common Practices (SCP)☆33Updated last year
- RISC-V Virtual Prototype☆44Updated 4 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆47Updated 3 weeks ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 5 months ago
- ☆44Updated 5 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- Open Source PHY v2☆31Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆21Updated last year
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Updated last week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- PCI Express controller model☆69Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated this week
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 9 months ago
- Hardware Formal Verification☆16Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆15Updated 8 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- A python based verilog parser☆20Updated 5 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- This shows a simple ARM bare-metal software implementation for gem5☆18Updated 4 years ago
- Qbox☆70Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year