diwu1990 / UnarySim
This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.
☆42Updated last year
Alternatives and similar repositories for UnarySim:
Users that are interested in UnarySim are comparing it to the libraries listed below
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 10 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- ☆26Updated last year
- ☆50Updated last month
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆25Updated 3 years ago
- ☆29Updated 4 months ago
- ☆27Updated 6 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- ☆39Updated 10 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Processing in Memory Emulation☆20Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆64Updated 2 weeks ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago
- ☆23Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- ☆11Updated 2 weeks ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- ☆10Updated 2 years ago