diwu1990 / UnarySimLinks
This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.
☆42Updated 2 years ago
Alternatives and similar repositories for UnarySim
Users that are interested in UnarySim are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- ☆25Updated 3 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆26Updated last year
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆32Updated this week
- Heterogenous ML accelerator☆18Updated last month
- Processing in Memory Emulation☆20Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- ☆53Updated 2 months ago
- ☆24Updated 4 years ago
- ☆35Updated 4 years ago
- ☆16Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- ☆29Updated 7 months ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆41Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- gem5 repository to study chiplet-based systems☆74Updated 6 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆9Updated last year
- ☆12Updated last month