huangxc6 / E203_CNN_Genesys2
Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
☆12Updated 9 months ago
Alternatives and similar repositories for E203_CNN_Genesys2:
Users that are interested in E203_CNN_Genesys2 are comparing it to the libraries listed below
- verilog实现TPU中的脉动阵列计算卷积的module☆77Updated 3 years ago
- AXI总线连接器☆94Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆31Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆137Updated 3 months ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- CPU Design Based on RISCV ISA☆89Updated 8 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆181Updated last year
- AXI协议规范中文翻译版☆138Updated 2 years ago
- Some useful documents of Synopsys☆62Updated 3 years ago
- 3×3脉动阵列乘法器☆38Updated 5 years ago
- ☆100Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆141Updated 8 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆62Updated 6 years ago
- IC implementation of Systolic Array for TPU☆189Updated 4 months ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- 数字IC秋招项目、手撕代码☆34Updated 10 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- IC Verification & SV Demo☆49Updated 3 years ago
- Convolutional Neural Network RTL-level Design☆44Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆36Updated 6 months ago
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- ☆114Updated last week
- SystemVerilog files for lab project on a DNN hardware accelerator☆15Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago
- syn script for DC Compiler☆12Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆77Updated 3 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆135Updated last year
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆32Updated last week