huangxc6 / E203_CNN_Genesys2
Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
☆11Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for E203_CNN_Genesys2
- AXI总线连接器☆91Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆31Updated 3 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆127Updated 5 months ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- 2023集创赛国二,紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆121Updated 2 weeks ago
- Convolutional accelerator kernel, target ASIC & FPGA☆167Updated last year
- 数字IC秋招项目、手撕代码☆33Updated 7 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆25Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago
- ☆93Updated 4 years ago
- IC implementation of Systolic Array for TPU☆152Updated last month
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- Convolutional Neural Network RTL-level Design☆34Updated 3 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆127Updated last year
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆121Updated 3 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆118Updated 7 months ago
- IC Verification & SV Demo☆45Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆166Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆71Updated 5 years ago
- commit rtl and build cosim env☆35Updated 7 months ago
- AXI协议规范中文翻译版☆132Updated 2 years ago
- ☆19Updated 10 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆160Updated 8 months ago