lauchinyuan / Booth4_wallace_MULT16_16Links
A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
☆48Updated 10 months ago
Alternatives and similar repositories for Booth4_wallace_MULT16_16
Users that are interested in Booth4_wallace_MULT16_16 are comparing it to the libraries listed below
Sorting:
- AXI总线连接器☆99Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month
- CPU Design Based on RISCV ISA☆113Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆157Updated last week
- Some useful documents of Synopsys☆75Updated 3 years ago
- AXI协议规范中文翻译版☆152Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- ☆65Updated 9 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- FFT generator using Chisel☆60Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- 基4booth乘法器设计与验证☆12Updated last year
- ☆163Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆211Updated 2 years ago
- ☆39Updated 4 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆90Updated 3 years ago
- IC implementation of Systolic Array for TPU☆251Updated 8 months ago
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆19Updated 2 years ago
- Open IP in Hardware Description Language.☆24Updated last year