lauchinyuan / Booth4_wallace_MULT16_16Links
A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
☆54Updated 11 months ago
Alternatives and similar repositories for Booth4_wallace_MULT16_16
Users that are interested in Booth4_wallace_MULT16_16 are comparing it to the libraries listed below
Sorting:
- AXI总线连接器☆103Updated 5 years ago
- CPU Design Based on RISCV ISA☆118Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- AXI协议规范中文翻译版☆159Updated 3 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆129Updated 3 months ago
- AXI DMA 32 / 64 bits☆116Updated 11 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆190Updated 9 months ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆118Updated 12 years ago
- An AXI4 crossbar implementation in SystemVerilog☆166Updated last month
- ☆68Updated 9 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- IC implementation of Systolic Array for TPU☆264Updated 9 months ago
- Convolutional Neural Network RTL-level Design☆66Updated 3 years ago
- ☆43Updated 4 years ago
- ☆52Updated 2 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated 11 months ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆25Updated 2 years ago
- ☆182Updated last month
- ☆43Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆93Updated 2 weeks ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆42Updated 2 years ago
- This is for uvm_tb_gen☆33Updated 5 months ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆93Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆214Updated 2 years ago