Alternatives and similar repositories for vim

Users that are interested in vim are comparing it to the libraries listed below

• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆25Updated 4 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆74Updated 4 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆38Updated last year
• hjking / uvm_gen
  UVM Generator
  ☆46Updated last year
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆55Updated 8 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆51Updated 10 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆68Updated 4 years ago
• muneeb-mbytes / uvm_tb_arch_doc_py
  A python project to automatically generate the UVM testbench document.
  ☆20Updated last year
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆40Updated 5 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 4 years ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆35Updated 10 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆23Updated 6 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• shady831213 / jarvisuk
  Just A Really Very Impressive Systemverilog UVM Kit
  ☆18Updated 4 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 7 months ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆78Updated 3 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆80Updated 8 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆58Updated 11 months ago
• designsolver / ahb3_uvm_tb
  AMBA 3 AHB UVM TB
  ☆32Updated 6 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆44Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆45Updated 9 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆16Updated 5 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆32Updated 4 years ago