mbits-mirafra / i3c_avipLinks
Verification IP project for I3C protocol
☆21Updated 9 months ago
Alternatives and similar repositories for i3c_avip
Users that are interested in i3c_avip are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆36Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Common SystemVerilog RTL modules for RgGen☆15Updated 3 months ago
- Structured UVM Course☆54Updated last year
- Open Source PHY v2☆31Updated last year
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- Simple single-port AXI memory interface☆48Updated last year
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆19Updated 5 years ago
- ☆37Updated 6 months ago
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- Testbenches for HDL projects☆22Updated last week
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- ☆43Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- SystemVerilog Logger☆19Updated 2 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆16Updated last month
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Verification IP for Watchdog☆12Updated 4 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆32Updated 5 years ago