Alternatives and similar repositories for i3c_avip

Users that are interested in i3c_avip are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆32Updated 4 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆21Updated 2 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆30Updated 7 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 2 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆40Updated 4 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated 2 weeks ago
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆34Updated 3 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆18Updated last month
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆21Updated last week
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆51Updated last year
• ADC-TEAM2020 / avsdadc_3v3
  This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…
  ☆20Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆11Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 5 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆91Updated 3 years ago
• mattvenn / pyfda-cocotb-demo
  Audio filtering with pyfda and cocotb
  ☆12Updated 5 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆24Updated 6 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• tchancarusone / Wireline-Simulink
  Basic Simulink Blocks for modeling CDRs and PLLs
  ☆13Updated 5 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆23Updated 10 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 7 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago