Edit SystemVerilog files (and UVM files) in Vim/gVim
☆30Mar 8, 2024Updated 2 years ago
Alternatives and similar repositories for verilog-support
Users that are interested in verilog-support are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆22Mar 12, 2024Updated 2 years ago
- UVM/systemverilog/verilog/python VIM IDE☆17Aug 21, 2013Updated 13 years ago
- UVM verification kits which uses YASA as simulation script☆19Dec 10, 2019Updated 6 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- verilog_instance.vim: create instantiation of ports from port declaration☆33Mar 13, 2023Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆151Jan 23, 2024Updated 2 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆426Aug 3, 2026Updated 3 months ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 3 years ago
- Verilog Implementation of Run Length Encoding for RGB Image Compression☆28Jun 28, 2021Updated 5 years ago
- System verilog register model for uvm testbenches.☆21Aug 29, 2018Updated 8 years ago
- A set of yasnippets for emacs that assist with SystemVerilog☆11Nov 25, 2011Updated 14 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆75Nov 22, 2019Updated 6 years ago
- SystemVerilog vim scripts☆69Jan 25, 2023Updated 3 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 10 years ago
- svlib from http://www.verilab.com/resources/svlib/☆27Jun 2, 2020Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Generate verilog register file from systemRDL description☆14Feb 9, 2024Updated 2 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 4 years ago
- The source code of blog☆14Dec 12, 2021Updated 4 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- SVA examples and demonstration☆19Sep 8, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Repo for CHERIoT-SAFE development FPGA platform☆21Sep 21, 2026Updated last month
- ☆16May 8, 2018Updated 8 years ago
- Verik toolchain☆47Dec 24, 2022Updated 3 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- ☆18Jan 7, 2023Updated 3 years ago
- SoC for CQU Dual Issue Machine☆12Sep 20, 2022Updated 4 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 9 years ago
- Just A Really Very Impressive Systemverilog UVM Kit☆17Dec 17, 2020Updated 5 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆136Nov 17, 2025Updated 11 months ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- ☆12May 31, 2016Updated 10 years ago
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- A generic class library in SystemVerilog☆91May 20, 2021Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆31Mar 21, 2017Updated 9 years ago