Language for simplifying parameterized RTL design
☆14Apr 3, 2026Updated 2 weeks ago
Alternatives and similar repositories for metahdl
Users that are interested in metahdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 6 months ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- Train a neural network to produce latex source code which generates a given pdf file☆13May 3, 2017Updated 8 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆12Jun 14, 2020Updated 5 years ago
- There is segmentation fault of VCS which should be fixed.☆44Sep 19, 2023Updated 2 years ago
- A terminal text editor written in MoonBit☆11Apr 7, 2025Updated last year
- A simple and naive WPF appliation that launches SSH daemon inside WSL☆11Jun 5, 2019Updated 6 years ago
- ☆11Mar 20, 2025Updated last year
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- CryptoCell 312 runtime code☆27Feb 3, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 8 years ago
- A Verilog-based Touhou derivative game, designed to run on physical FPGA development boards with VGA output for display.☆10Feb 19, 2026Updated last month
- Translates the DSD/DSF file into WAV file written in C for learning,☆11Feb 21, 2019Updated 7 years ago
- ARM4U☆34Jul 17, 2014Updated 11 years ago
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆30May 30, 2020Updated 5 years ago
- typecho1.2版本已支持文章左右预览，本项目停止维护☆12Dec 28, 2015Updated 10 years ago
- ☆17Mar 13, 2026Updated last month
- ☆11Jul 4, 2016Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 9 years ago
- This is the paddle code for SeBoW(Self-Born wiring for neural trees), a kind of neural tree born form a large search space☆11Dec 10, 2021Updated 4 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 6 years ago
- Wraps the NVDLA project for Chipyard integration☆23Sep 2, 2025Updated 7 months ago
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆15Oct 5, 2023Updated 2 years ago
- ☆12Oct 31, 2024Updated last year
- ☆11Nov 24, 2020Updated 5 years ago
- Implementations of the compilers and VMs from R. Kent Dybvig's "Three Implementation Models for Scheme." Each file is named after the se…☆24Apr 22, 2010Updated 15 years ago
- Repo for CHERIoT-SAFE development FPGA platform☆20Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Fork from 103yiran/XDUthesis_xelatex and modified☆12Mar 27, 2019Updated 7 years ago
- website of mooncakes.io, written in MoonBit☆24Apr 2, 2026Updated 2 weeks ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- Explore words and the zeitgeist (as mediated by Google's search suggestions)☆16Dec 23, 2025Updated 3 months ago
- InnovateFPGA☆14Apr 30, 2018Updated 7 years ago