Language for simplifying parameterized RTL design
☆14Apr 3, 2026Updated 3 months ago
Alternatives and similar repositories for metahdl
Users that are interested in metahdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 10 months ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆12Jun 14, 2020Updated 6 years ago
- Train a neural network to produce latex source code which generates a given pdf file☆13May 3, 2017Updated 9 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 7 years ago
- There is segmentation fault of VCS which should be fixed.☆46Sep 19, 2023Updated 2 years ago
- A terminal text editor written in MoonBit☆10Apr 7, 2025Updated last year
- A simple and naive WPF appliation that launches SSH daemon inside WSL☆11Jun 5, 2019Updated 7 years ago
- ☆12Mar 20, 2025Updated last year
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 12 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- CryptoCell 312 runtime code☆27Feb 3, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- This is the paddle code for SeBoW(Self-Born wiring for neural trees), a kind of neural tree born form a large search space☆11Dec 10, 2021Updated 4 years ago
- A Verilog-based Touhou derivative game, designed to run on physical FPGA development boards with VGA output for display.☆10Feb 19, 2026Updated 5 months ago
- ARM4U☆34Jul 17, 2014Updated 12 years ago
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 9 years ago
- Translates the DSD/DSF file into WAV file written in C for learning,☆11Feb 21, 2019Updated 7 years ago
- Extension support for VS Code Embedded Debug Extension☆13Apr 16, 2026Updated 3 months ago
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆30May 30, 2020Updated 6 years ago
- This software pack enables developers to develop and deploy neural networks on MCU-based systems for building smart sensing applications.…☆17Jul 30, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- typecho1.2版本已支持文章左右预览，本项目停止维护☆12Dec 28, 2015Updated 10 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆32Oct 9, 2020Updated 5 years ago
- ☆11Jul 4, 2016Updated 10 years ago
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 10 years ago
- Linux development repository for socfpga☆16May 27, 2026Updated 2 months ago
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆16Oct 5, 2023Updated 2 years ago
- ☆12Oct 31, 2024Updated last year
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated 10 months ago
- ☆11Nov 24, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Fork from 103yiran/XDUthesis_xelatex and modified☆12Mar 27, 2019Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Explore words and the zeitgeist (as mediated by Google's search suggestions)☆16Dec 23, 2025Updated 7 months ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- Another dumb attempt to build ancient emacs-18.59 on the latest NetBSD (and Linux), based on Gentoo Portage patches and my mule1.1-netbsd…☆15Jul 6, 2026Updated 3 weeks ago
- A simple PDM microphone interface on FPGA☆15Jan 16, 2022Updated 4 years ago