keyonhome / AXI4_LiteIPLinks
A verilog FPGA Interface for AXI4_Lite from Slave side
☆11Updated 5 years ago
Alternatives and similar repositories for AXI4_LiteIP
Users that are interested in AXI4_LiteIP are comparing it to the libraries listed below
Sorting:
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16Updated 4 years ago
- AXI4 BFM in Verilog☆35Updated 9 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆85Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago
- AXI DMA 32 / 64 bits☆124Updated 11 years ago
- AXI总线连接器☆105Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆26Updated 7 years ago
- A verilog implementation for Network-on-Chip☆80Updated 8 years ago
- PCIE 5.0 Graduation project (Verification Team)☆100Updated 2 years ago
- AXI Interconnect☆56Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆160Updated 7 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆136Updated 4 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆136Updated 8 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆72Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Verification IP for APB protocol☆75Updated 5 years ago
- VIP for AXI Protocol☆163Updated 3 years ago
- UVM AHB VIP☆93Updated 4 months ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Updated 3 years ago
- ☆74Updated 10 years ago
- round robin arbiter☆78Updated 11 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- ahb scram controller, design and verification☆28Updated 7 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…